Controlling Memory Traffic on
Intel® Xeon Phi™ Processors
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Controlling Memory Traffic on Intel® Xeon Phi™ Processors
Is your code optimized for maximum performance? Multi-level parallelism can help your code achieve its potential and accelerate your path to innovation. In this hour-long webinar, HPC Expert Andrey Vladimirov will introduce two aspects of memory traffic tuning in computational applications on Intel® Xeon Phi™ Processors, maximizing cache utilization, and streamlining access to the main memory.
This presentation will cover:
- Programming techniques for data locality improvement in loops.
- Permutation, fusion, tiling; and recipes for optimizing memory bandwidth.
- Unit-stride access, thread affinity settings, and allocation in high-bandwidth memory (HBM) using programmatic and automatic approaches.
Speaker
Andrey Vladimirov, PhD
Head of HPC Research at Colfax International
Prior to joining Colfax, Andrey Vladimirov was involved in computational astrophysics research at Stanford University, North Carolina State University, and the Ioffe Institute (Russia), where he studied cosmic rays, collisionless plasmas and the interstellar medium using computer simulations. He is the lead author of a book on parallel programming and optimization, author of over 25 research publications at the online resource Colfax Research and more than 10 invited, peer-reviewed and contributed papers in industry-leading publications in scientific computing and astrophysics.