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Unleash your Code's Potential using Vector Programming best practices

In recent CPU product generations, HW investments in SIMD technology grew significantly. Consistent with the growth in HW support, the performance requirements grow as well. Learn why the increased vector performance potential justifies greater attention to application code design.

During this webinar, Intel Principal Engineer and Modern Code expert Robert Geva shows how the OpenMP 4.0 solution allows the programmer to write C/C++ code using OpenMP directives to express vector semantics in order to achieve those desired performance results. The webinar introduces the new syntax and shows several best practices for using it. In addition, Geva shows what a similar capability would look like to support C++ standards, and which is designed to apply to both vector loops and STL algorithms. Webinar attendees will also learn about some pitfalls of expecting performance portability across CPUs and GPUs, and highlights of how design consideration for CPU vectorization differs from that of GPGPU programming. You will walk away with an understanding of recommended techniques for your code in order to attain maximum performance and make full use of today’s and tomorrow’s hardware.

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Speakers

Robert Geva

Principal Engineer, Intel® Software and Services Group

Robert is a principal engineer at Intel's software and services group. His current role is the manager of the financial services engineering group, where he leads a team of SW engineers working with customers in FSI. Robert joined Intel in 1991 and has since developed an expertise in compilers and performance analysis and tuning for microarchitectures. Robert has worked on compiler optimizations for a variety of Intel microprocessor based systems, including the 80486, the Intel® Pentium® Processor, the Intel® Pentium® Processor, Intel® Itanium®, the Intel® Pentium® 4 and Pentium® M and cIntel® Core™2 Duo Processor. Most recently, Robert was an architect in the development products division responsible for driving language extensions and programming models for parallel and heterogeneous programming. Robert has been involved with the development of Intel Cilk™ Plus and the offloading model for Intel® Xeon® Phi™. Robert has BA and MSc from the Technion, Israel institute of technology.